This invention relates generally to integrated circuit structures and manufacturing methods and more particularly to methods used in the manufacture of bipolar transistor devices and junction field effect transistor (JFET) devices on a common single crystal substrate.
As is known in the art, one technique used to form a buried channel JFET device is to ion implant particles into an epitaxial layer, spaced from the surface thereof, and extending between the source and drain regions, such particles being capable of forming a doped buried channel region having opposite type conductivity from the conductivity type of the epitaxial layer. An insulating layer is then formed over the surface of the epitaxial layer with opening formed therein to allow for source, gate and drain contacts. With such arrangement, since a portion of the epitaxial layer extends from the upper portion of the buried channel region to the insulating layer the doping concentration of the epitaxial layer must be sufficiently high, on the one hand, to prevent undesirable surface state inversion effects and must be sufficiently low, on the other hand, to provide the device with adequate breakdown voltage characteristics. To meet these conflicting requirements is, however, difficult.
One technique used to balance these conflicting requirements of breakdown voltage and surface state inversion is to provide a so-called "heavy top gate region" between the surface of the epitaxial layer and the buried channel region, such heavy top gate region having the same conductivity type as that of the epitaxial layer, but with a doping concentration much larger than that of both the epitaxial layer and the buried channel region. The heavy top gate region is, however, spaced from the source and drain regions. In this way the device will have a sufficiently high doping concentration in the heavy top gate region to prevent surface state inversion effects and, since such heavy top gate region is spaced from the source and drain regions (hence separated from such regions by portions of the more lightly doped epitaxial layer), the device will have adequate breakdown voltage characteristics. While such technique may provide a way of meeting the conflicting requirements of breakdown voltage and surface state inversion effects in the field effect device region, such technique requires an additional masking step, i.e., the step necessary to place the heavy top gate region accurately spaced from the source and drain regions, thereby complicating the manufacturing process and reducing device yield.
Another technique suggested to meet the conflicting requirements of surface state inversion effects and device breakdown voltage is to provide a moderately doped layer of semiconductor material between the surface of the epitaxial layer and the ion implanted buried channel region, such moderately doped layer having the same type conductivity as the epitaxial layer, but having a doping concentration slightly larger than, typically five times larger than, the doping concentration of the epitaxial layer but less than the doping concentration of the heavy top gate region described above. In this way the moderately doped region may extend laterally along the surface of the epitaxial layer through both the source and drain regions since its doping concentration level is sufficiently low to produce the desired breakdown voltage characteristics for the device and sufficiently high to provide adequate protection against surface state inversion over the field effect device region. When it is desired to produce both JFET devices and bipolar transistor devices on the same chip, however, a masking step has been used to prevent the moderately doped region from being formed in the regions of the chip where the bipolar devices are formed.